1. Field of the Invention
The present invention relates to a communication apparatus configured using a logic circuit with a changeable circuit configuration.
2. Description of the Related Art
In recent years, progress made in cloud computing and the internet of things (IoT) has led to the diversification of services provided via networks and, consequently, devices related to various services are being connected to networks. Whereas a dedicated communication apparatus or a dedicated network has been conventionally constructed for each service, in order to integrate and accommodate a variety of services, studies on virtualization technology are underway to construct a virtual machine which performs processing corresponding to each service on a general-purpose server or, more specifically, on a CPU of a general-purpose server.
Meanwhile, with the diversification of businesses and services, the capacity of traffic in communication systems is increasing and limits in software processing performances of CPUs have become a concern. In consideration thereof, hardware offload which enhances performance by extracting part of software processing and processing the extracted part by hardware is being studied.
Utilization of hardware offload is already underway in data retrieval by cloud providers and the like and, in the future, it is anticipated that there will be a greater need to offload various functions on hardware and improve processing performance of each function.
A field-programmable gate array (FPGA) is attracting attention as hardware with high processing performance per power consumption in realizing hardware offload. An FPGA enables an entire or a partial circuit configuration to be configured or changed by writing a circuit file describing circuit configuration information in accordance with a function to be realized by the FPGA. An operation of writing a circuit file to an FPGA is referred to as configuration. Even after an FPGA is manufactured, it is possible to configure or change a circuit configuration of the FPGA by a purchaser or a designer performing the configuration. For example, a logic circuit can be programmed on site.
Prior art regarding programmable hardware such as an FPGA include the following.
Japanese Patent Application Laid-open No. 2000-252814 discloses a technique involving storing in advance, in storage means, information of a plurality of hardware modules (hereinafter, also simply referred to as “modules”) of which physical shapes on a programmable logic circuit differ from one another when reconfigured on the logic circuit, and preferentially using a module matching a shape of a free area in the programmable logic circuit when performing partial rewriting. A circuit area can be efficiently utilized by using a module matching a shape of the free area.
Japanese Patent Application Laid-open No. 2010-171994 discloses a dynamic reconfiguration technique of a logic circuit, the technique involving providing, in advance, an arithmetic core including a selector to which is input multi-bit function codes respectively indicating a logic operation and which selects output data based on input data, and supplying a function code to an arithmetic core to change an operation.
With the technique described in Japanese Patent Application Laid-open No. 2010-171994, since logic can be changed by a function code, the time required for reconfiguration can be reduced as compared to hardware such as an FPGA which stores a configuration of a circuit in a lookup table (LUT). Accordingly, only a circuit required in each instant can be dynamically generated in hardware space as a circuit instance.
A data processing apparatus including a logic circuit that is reconfigurable due to the technique described in Japanese Patent Application Laid-open No. 2010-171994 enables an allocation of a hardware resource to an urgently required function to be increased and an allocation of a hardware resource to a function not required urgently to be reduced, even during use of the apparatus.